The present invention relates to an integrated memory having a memory cell array having memory cells connected to word lines and bit lines, in which the memory cell array is subdivided into a plurality of separate segments with respective local word lines, and also to a method for operating the memory.
An integrated memory such as, for example, a dynamic random access memory (DRAM) generally has a memory cell array containing bit lines and word lines. In this case, the memory cells are disposed at crossover points between the bit lines and word lines. The memory cells are connected to one of the bit lines and one of the word lines. For the selection of one of the memory cells, the corresponding word line is activated via a row decoder, as a result of which a data signal of a memory cell can subsequently be read out or written via the bit line selected via a column decoder.
In order to activate the word lines as rapidly as possible, the word lines are constructed in a multilayer manner, for example in this case, each word line has first conductive structures and second conductive structures disposed in respectively difference wiring planes of the memory. The different wiring planes are formed by conductive layers of the memory that are disposed one above the other or one below the other. In this case, the first conductive structures are usually realized by a metal, and the second conductive structures by polysilicon. While the first conductive structures are essentially embodied in one piece, the second conductive structures are disposed such that they are subdivided into a plurality of segments and each of these local word lines is connected to the associated first conductive structure via a corresponding plated-through hole. In this case, the second conductive structures are connected to the memory cells.
Local driver circuits are often provided for addressing memory cells. Depending on an activation state of the word line or of the first conductive structures thereof, the driver circuits connect the corresponding word line segment or the second conductive structures to a voltage source for providing a supply potential.
It is possible to achieve a high activation speed of a word line by providing driver circuits having particularly great dimensions. This usually results in a high outlay in respect of space on the memory chip. It is equally possible to achieve a high activation speed of a word line by technologically comparatively complex measures such as reducing the sheet resistance of word lines made of polysilicon. For this purpose, by way of example, a metal interconnect is routed parallel to a polysilicon interconnect. This gives rise to the requirement of providing at least two wiring planes, as described above.
It is accordingly an object of the invention to provide an integrated memory having a memory cell array with a plurality of segments and a method for operating the integrated memory which overcomes the above-mentioned disadvantages of the prior art devices and methods of this general type, which allows a word line to be activated as fast as possible and in a manner that saves as much current as possible.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory. The integrated memory contains a row decoder, a column decoder for receiving a column address, word lines, bit lines, and a memory cell array having memory cells connected to the word lines and to the bit lines. The memory cell array is subdivided into a plurality of separate segments including a first segment and a second segment. The word lines each have local word lines including a first local word line disposed in the first segment and a second local word line disposed in the second segment. The first local word line and the second local word line together form a common global word line decoded by the row decoder. The first and second local word lines are connected up to the column decoder such that the first and second local word lines are decoded individually and segment by segment in a manner dependent on the column address.
The integrated memory has the first local word line in the first segment of the memory cell array and the second local word line in the second segment, the first and second local word lines form the common global word line. In this case, the global word line is decoded via a row decoder. The first and second local word lines are additionally connected up to a column decoder in such a way that they can be decoded individually and segment by segment in a manner dependent on a column address. In other words, the respective word line segments or the corresponding local word lines can advantageously be activated only when they are actually required during a read or write access. This is made possible by the use of a column address during the decoding of a word line segment or of a local word line.
It is thereby possible to achieve a higher activation speed for the activation of a word line, since, with the selection only of a local word line in a segment, the effective load on the word line decoder can be kept comparatively low. Moreover, a comparatively low current consumption is made possible since, in an access cycle, only a part of the word line and, in connection therewith, a smaller number of word line drivers is activated.
Accordingly, in a method for operating the memory according to the invention, within an access cycle, depending on the column address, only the first or second local word line is activated for a memory cell access.
It is advantageous particularly for a so-called refresh operation of the integrated memory if it is possible to select between two operating modes of the memory. In the event of a refresh being carried out as fast as possible, in a first operating mode, within the access cycle, depending on the column address, the first and second local word lines and thus two word line segments are simultaneously activated for a memory cell access. If, in contrast thereto, the desire is to achieve a minimum peak current in a refresh operation, in a second operating mode the respective local word lines in a segment are activated in each case in a temporally staggered manner. A similar operating mode is also advantageous for a normal operation in which, during a memory cell access, an entire row is opened in a so-called open page mode. Temporally staggered driving of the word line segments enables the peak current to be kept low in normal operation.
In an advantageous embodiment of the memory according to the invention, the memory has a main word line, which runs via the segments of the memory cell array. The main word line drives an associated local word line in a respective one of the segments. For the decoding, depending on a column address, a supply potential terminal of each local word line can be connected to a line for a supply potential in a decodable manner via the column decoder.
In accordance with an added feature of the invention, a number of the local word lines are disposed in each of the segments. The main word line drives the number of the local word lines in a respective one of the segments. The supply potential terminal of each of the local word lines can be connected to the global line in a decodable manner in dependence on the row decoder and the column decoder.
In accordance with a further feature of the invention, voltage supply lines run in the segments and are controllably coupled to the global line. Driver circuits connect the main word line to the local word lines in each of the segments. Each of the driver circuits has a control input connected to the main word line, and each of the driver circuits has a driver voltage supply terminal connected to one of the voltage supply lines in a respective one of the segments. The voltage supply lines are controllably coupled to and uncoupled from the global line in dependence on the column decoder.
In accordance with another feature of the invention, a logic circuit is connected between the global line associated with all of the segments and the voltage supply lines. The logic circuit has a control input connected to and controlled by the column decoder. The logic circuit couples the global line to the voltage supply lines.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory having a memory cell array with a plurality of segments and method for operating the integrated memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.